The Chip - Southbridge and Northbridge

The chip set

The motherboard’s busses are regulated by a number of controllers. These are small circuits which have been designed to look after a particular job, like moving data to and from EIDE devices (hard disks, etc.).

A number of controllers are needed on a motherboard, as there are many different types of hardware devices which all need to be able to communicate with each other. Most of these controller functions are grouped together into a couple of large chips, which together comprise the chip set.

Figure 44. The two chips which make up the chipset, and which connect the motherboard’s busses.

The most widespread chipset architecture consists of two chips, usually called the north and south bridges. This division applies to the most popular chipsets from VIA and Intel. The north bridge and south bridge are connected by a powerful bus, which sometimes is called a link channel:

Figure 45. The north bridge and south bridge share the work of managing the data traffic on the motherboard.

The north bridge

The north bridge is a controller which controls the flow of data between the CPU and RAM, and to the AGP port.

In Fig. 46  you can see the north bridge, which has a large heat sink attached to it. It gets hot because of the often very large amounts of data traffic which pass through it. All around the north bridge you can see the devices it connects:

Figure 46. The north bridge and its immediate surroundings. A lot of traffic runs through the north bridge, hence the heat sink.

The AGP is actually an I/O port. It is used for the video card. In contrast to the other I/O devices, the AGP port is connected directly to the north bridge, because it has to be as close to the RAM as possible. The same goes for the PCI Express x16 port, which is the replacement of AGP in new motherboards. But more on that later.

The south bridge

The south bridge incorporates a number of different controller functions. It looks after the transfer of data to and from the hard disk and all the other I/O devices, and passes this data into the link channel which connects to the north bridge.

In Fig. 44 you can clearly see that the south bridge is physically located close to the PCI slots, which are used for I/O devices.

Figure 47. The chipset’s south bridge combines a number of controller functions into a single chip.